On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications
This book deals with modeling of defects that are introduced into integrated circuits during manufacturing and design methods aimed at increasing the testability of modern circuits. First, several modeling and simulation techniques for short defects are introduced, ranging from low-cost models to sophisticated systems that take the defect resistance into account. The latter parameter is increasingly relevant for deep submicron technology. Also, an application in an industrial setting is reported. The second part of the book describes circuit design approaches that help to detect dynamic defects that impact the timing of a circuit but not its function. These importance of these defects is steadily growing, but they are not adequately covered by conventional test methods. A scan design method and a Built-In Self Test block that can distribute the test complexity between on-chip structures and automatic test equipment are proposed. Finally, two appendices study the relationship between non-standard fault models and the conventional stuck-at model and their use for formal verification.