Power Distribution Networks with On-Chip Decoupling Capacitors
This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this second edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.
Describes power distribution systems and related design problems, including both circuit models and design techniques to allocate on-chip decoupling capacitorsDetails effects of inductance on impedance characteristics of on-chip power distribution gridsIncludes new material on inductance models for interdigitated structures, design strategies for multi-layer power grid networks, and advanced algorithms for computational power grid analysis