Pipelined Multiprocessor System-on-Chip for Multimedia
This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.
Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCsIncludes analytical models and estimation methods for performance estimation of pipelined MPSoCsCovers several design space exploration techniques for pipelined MPSoCsIntroduces an adaptive pipelined MPSoC with run-time processor and power managersIntroduces Multi-mode pipelined MPSoCs for multiple applications